The present invention relates to a memory circuit, and more particularly relates to a memory circuit that includes a circuit for detecting or correcting soft errors in stored data.
In recent years, as semiconductor memory fabrication process has been microscaled, the area of a single memory cell has been continuously reduced. Along with this, the amount of electric charge accumulated in a memory cell has also been reduced. As a result, the flow of electric charge into the memory cell and the resulting data corruption, caused by incoming alpha radiation and cosmic rays, are becoming serious problems. The data corruption occurs due to changes in the potential of a storage node in the memory cell caused by the flow of electric charge into the storage node, and the memory cell is not physically broken. Therefore, the error can be corrected by a rewrite of correct data at the same address. This kind of error is called a soft error. A soft error is typically dealt with by an error check and correct circuit (ECC circuit).
In a memory circuit including a conventional error check and correct circuit, at the time of data input into the memory, redundant data such as a Hamming code is added and stored together with the main data, and at the time of data output from the memory, the main data and the redundant data are used to reconstruct the input data. For example, if, at the time of input of 32-bit data, 6-bit redundant data using a Hamming code is stored, a 1-bit data error occurring during the data-storing process can be corrected when the data is output (see “A Built-In Hamming Code ECC Circuit for DRAM's” by Kiyohiro FURUTANI et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, (U.S.A) pp. 50-56, Issue No. 1, Vol. 24, February 1989).
FIG. 4 is a block diagram showing an example of the structure of a conventional memory circuit. The memory circuit of FIG. 4 includes a data storage section 900, an error correction section 920, and an input buffer 932. The data storage section 900 includes a data memory cell array 902, a redundant data memory cell array 904, an address decoder 906, and a control signal input circuit 912. The error correction section 920 includes a coding circuit 924 and an output data error check and correct circuit 928.
FIG. 5 is a circuit diagram showing the structure of the control signal input circuit 912 of FIG. 4. The control signal input circuit 912 includes flip flops 941 and 942 and logic gates 951 and 952.
Data input/output into/from the data storage section 900 is performed in synchronization with a rising edge of a clock signal CLK. When a read/write control signal NWE is at a low potential (which will be hereinafter referred to as the “L” level), the control signal input circuit 912 activates an internal write control signal IWE in synchronization with the clock signal CLK. That is, the control signal input circuit 912 sets the internal write control signal IWE at a high potential (which will be hereinafter referred to as the “H” level). When a memory selection signal NCS is at the “L” level, the control signal input circuit 912 outputs the clock signal CLK as an internal clock signal ICLK.
FIG. 6 is a timing chart showing an example of the operation of the memory circuit of FIG. 4. In FIG. 6, an address signal A is input into the memory circuit at the rising edge of the internal clock signal ICLK, and the address decoder 906 decodes the address signal A and generates a signal AIN for selecting stored data.
The cycle 1 shown in FIG. 6 is a write cycle. Since the read/write control signal NWE goes to the “L” level, the control signal input circuit 912 of FIG. 5 activates the internal write control signal IWE in synchronization with the clock signal CLK.
Then, the input buffer 932 outputs external input data D as internal input data DIN. The internal input data DIN is written into the data memory cell array 902. The coding circuit 924 generates a Hamming code for error correction based on the internal input data DIN and outputs the generated code as redundant data PIN. The redundant data PIN is written into the redundant data memory cell array 904.
The cycles 2 to 4 are read cycles. If the internal write control signal IWE is not activated at a rising edge of the clock signal CLK, the data memory cell array 902 and the redundant data memory cell array 904 output internal output data DOUT and redundant data POUT, respectively, to the output data error check and correct circuit 928.
The output data error check and correct circuit 928 uses the redundant data POUT to perform error correction for the internal output data DOUT and makes a comparison between the corrected data and the read internal output data DOUT so as to detect whether or not an error is contained. Upon detection of an error, the output data error check and correct circuit 928 sets an error detection signal ERR to the “H” level and outputs the error detection signal ERR, and outputs error-corrected output data Q outside the memory circuit.
However, there is a problem with the conventional error check and correct circuit, because the error check and correct circuit is disposed in the data output path, which causes the memory's output access time to be very long as compared with a case in which no error check and correct circuit is provided. Specifically, as shown in FIG. 6, the internal output data DOUT always passes through the error check and correct circuit before it is output as the external output data Q, thereby causing the output access time to be increased.